Configures a device on this SPI bus.
The device's clock speed is configured to the given frequency. The given frequency is only aspirational, and the actual frequency might be different. For example, the ESP32S3 seems to have a minimum frequency of 100kHz.
An optional cs (chip select) and dc (data/command) pin can be assigned for this device. They are GPIO numbers. The device reserves the pins and releases them again when the device is closed. If no cs pin is provided, then the chip must be enabled in software (or hardware, tied to ground, if it's the only chip on the bus).
The SPI mode can further be configured in the range [0..3], defaulting to 0.
Some SPI devices have an explicit command and/or address section that can be configured using command-bits and address-bits.
Parameters
The mode parameter configures the clock polarity and phase (CPOL and CPHA) for this bus.
The possible configurations are:
0 (0b00): CPOL=0, CPHA=0
1 (0b01): CPOL=0, CPHA=1
2 (0b10): CPOL=1, CPHA=0
3 (0b11): CPOL=1, CPHA=1
Passing a gpio.Pin as cs or dc is deprecated; provide the integer GPIO number instead. The gpio.Pin form will be removed in a future release. cs-setup-cycles requests that CS be active for the given number of SPI clock cycles before the first clock edge. ESP-IDF only supports this option for half-duplex transactions, except for a limited one-cycle case on the classic ESP32. cs-hold-cycles keeps CS active after the last clock edge. Setup must be between 0 and 16. Hold must be between 0 and 16, except on the classic ESP32 where the maximum is 15.
On ESP32, a bus configured with only one of mosi and miso registers its devices as half-duplex. A bus with both data pins remains full-duplex.
The bus retains the returned device until either the device or the bus is explicitly closed. Dropping the last application reference does not free a device slot while its bus remains open.